/*
share header file for kern_drv & usr_app
*/
#ifndef _IOCTL_DRV_USR_H_
#define _IOCTL_DRV_USR_H_

#if 1
#define BUFFER_LENGTH  256

#define IO_GET_DRV_VER         (0xaa00)
#define IO_GET_RD_DDR_TEST     (0xaa01)

#define IO_GET_RD_DDR_DATA     (0xaa02)
#define IO_GET_RD_DDR_DATA2    (0xaa03)

#define IO_GET_IRQ_CHN_NO      (0xaa04)
#define IO_GET_DDR_PHY_ADDR    (0xaa05)


//-------------------------------------
#define IO_SET_SND_DATA        (0xbb10)
#define IO_SET_WR_DDR_DATA     (0xbb11)
#define IO_SET_CLR_DDR_TEST    (0xbb12)

#define IO_SET_TX_FPGA_CH1       (0xbb13)
#define IO_SET_TX_FPGA_CH2       (0xbb14)
#define IO_SET_TX_FPGA_CH3       (0xbb15)
#define IO_SET_TX_FPGA_CH4       (0xbb16)

#define IO_TEST_TRIG_IRQ         (0xbb17)
#define IO_TEST_RD_IRQ_TIME      (0xbb18)
#endif


#define BUF_SIZE  (256)   // 0x200000 -> 256

typedef struct  
{
	unsigned long addr;
	unsigned char buf[BUF_SIZE];
} T_DDR_DATA;


#define SIZE_1M       (0x100000)
#define SIZE_2M       (0x200000)
#define SIZE_3M       (0x300000)
#define SIZE_4M       (0x400000)
#define SIZE_5M       (0x500000)
#define SIZE_8M       (0x800000)
#define SIZE_12M      (0xC00000)
#define SIZE_16M     (0x1000000)


#if 1
/*
-----------------------------1. ��ʼ����--------------------------------------
���ں�FPGA��·��ʼ����link��ɣ����ÿռ�ʹ��busmaster,msi enable
����Ϊ7��ͨ������Ŀ�ĵ�ַDMA_WR_DST_ADDR_CHX
DMA_DST_CH1_HIGH(0X34) + DMA_DST_CH1_LOW(0X04)
DMA_DST_CH2_HIGH(0X48) + DMA_DST_CH2_LOW(0X44)
DMA_DST_CH3_HIGH(0X58) + DMA_DST_CH3_LOW(0X54)
DMA_DST_CH4_HIGH(0X68) + DMA_DST_CH4_LOW(0X64)
DMA_DST_CH5_HIGH(0X78) + DMA_DST_CH5_LOW(0X74)
DMA_DST_CH6_HIGH(0X88) + DMA_DST_CH6_LOW(0X84)
DMA_DST_CH7_HIGH(0X98) + DMA_DST_CH7_LOW(0X94)

��������DMA_WR_CMD_CHX(0x00)�Ĵ���,д0x1����ʾ����DMAд��
DMA_WR_CMD_CH1(0x00) 
DMA_WR_CMD_CH2(0x40) 
DMA_WR_CMD_CH3(0x50) 
DMA_WR_CMD_CH4(0x60) 
DMA_WR_CMD_CH5(0x70) 
DMA_WR_CMD_CH6(0x80) 
DMA_WR_CMD_CH7(0x90) 
*/
// chn-1
#define DMA_DST_CH1_1_HIGH  (0X34)
#define DMA_DST_CH1_1_LOW   (0X04)

#define DMA_DST_CH1_2_HIGH  (0X108) //+ 
#define DMA_DST_CH1_2_LOW   (0X104)

#define DMA_DST_CH1_3_HIGH  (0X118) //+ 
#define DMA_DST_CH1_3_LOW   (0X114)

#define DMA_DST_CH1_4_HIGH  (0X128) //+ 
#define DMA_DST_CH1_4_LOW   (0X124)

// chn-2
#define DMA_DST_CH2_1_HIGH  (0X48)
#define DMA_DST_CH2_1_LOW   (0X44)

#define DMA_DST_CH2_2_HIGH  (0X208) //+ 
#define DMA_DST_CH2_2_LOW   (0X204)

#define DMA_DST_CH2_3_HIGH  (0X218) //+ 
#define DMA_DST_CH2_3_LOW   (0X214)

#define DMA_DST_CH2_4_HIGH  (0X228) //+ 
#define DMA_DST_CH2_4_LOW   (0X224)

// chn-3
#define DMA_DST_CH3_1_HIGH  (0X58)
#define DMA_DST_CH3_1_LOW   (0X54)

#define DMA_DST_CH3_2_HIGH  (0X308) //+ 
#define DMA_DST_CH3_2_LOW   (0X304)

#define DMA_DST_CH3_3_HIGH  (0X318) //+ 
#define DMA_DST_CH3_3_LOW   (0X314)

#define DMA_DST_CH3_4_HIGH  (0X328) //+ 
#define DMA_DST_CH3_4_LOW   (0X324)

// chn-4
#define DMA_DST_CH4_1_HIGH  (0X68)
#define DMA_DST_CH4_1_LOW   (0X64)

#define DMA_DST_CH4_2_HIGH  (0X408) //+ 
#define DMA_DST_CH4_2_LOW   (0X404)

#define DMA_DST_CH4_3_HIGH  (0X418) //+ 
#define DMA_DST_CH4_3_LOW   (0X414)

#define DMA_DST_CH4_4_HIGH  (0X428) //+ 
#define DMA_DST_CH4_4_LOW   (0X424)

// chn-5
#define DMA_DST_CH5_1_HIGH  (0X78)
#define DMA_DST_CH5_1_LOW   (0X74)

#define DMA_DST_CH5_2_HIGH  (0X508) //+ 
#define DMA_DST_CH5_2_LOW   (0X504)

#define DMA_DST_CH5_3_HIGH  (0X518) //+ 
#define DMA_DST_CH5_3_LOW   (0X514)

#define DMA_DST_CH5_4_HIGH  (0X528) //+ 
#define DMA_DST_CH5_4_LOW   (0X524)

// chn-6
#define DMA_DST_CH6_1_HIGH  (0X88)
#define DMA_DST_CH6_1_LOW   (0X84)

#define DMA_DST_CH6_2_HIGH  (0X608) //+ 
#define DMA_DST_CH6_2_LOW   (0X604)

#define DMA_DST_CH6_3_HIGH  (0X618) //+ 
#define DMA_DST_CH6_3_LOW   (0X614)

#define DMA_DST_CH6_4_HIGH  (0X628) //+ 
#define DMA_DST_CH6_4_LOW   (0X624)

// chn-7
#define DMA_DST_CH7_1_HIGH  (0X98)
#define DMA_DST_CH7_1_LOW   (0X94)

#define DMA_DST_CH7_2_HIGH  (0X708) //+ 
#define DMA_DST_CH7_2_LOW   (0X704)

#define DMA_DST_CH7_3_HIGH  (0X718) //+ 
#define DMA_DST_CH7_3_LOW   (0X714)

#define DMA_DST_CH7_4_HIGH  (0X728) //+ 
#define DMA_DST_CH7_4_LOW   (0X724)


#define DMA_WR_CMD_CH1  (0x00) 
#define DMA_WR_CMD_CH2  (0x40) 
#define DMA_WR_CMD_CH3  (0x50) 
#define DMA_WR_CMD_CH4  (0x60) 
#define DMA_WR_CMD_CH5  (0x70) 
#define DMA_WR_CMD_CH6  (0x80) 
#define DMA_WR_CMD_CH7  (0x90) 


/*
f.���ڶ�ȡ֡ͨ������Ϣ��
DMA_WR_CHANNEL(0xa0) 

g.���ڸ���֡ͨ���ţ������µ�Ŀ�ĵ�ַ�Ĵ�������������ѭ����Ӧ����ַ���������й�����
h.����������֪ͨӦ�ò㴦�����ݡ�
*/
#define DMA_WR_CHANNEL   (0xa0) 
#endif

#if 1
/*
3.��������4��ͨ���Ķ�BUF��ʼ��ַ (ft --> fpga)

dma_rd_ch1_1_64bit = dma_rd_ch1_1_H(0x38)  + dma_rd_ch1_1_L(0x14)
dma_rd_ch1_2_64bit = dma_rd_ch1_2_H(0x188) + dma_rd_ch1_2_L(0x184)
dma_rd_ch1_3_64bit = dma_rd_ch1_3_H(0x198) + dma_rd_ch1_3_L(0x194)
dma_rd_ch1_4_64bit = dma_rd_ch1_4_H(0x1a8) + dma_rd_ch1_4_L(0x1a4)
*/
#define dma_rd_ch1_1_H  (0x38)
#define dma_rd_ch1_1_L  (0x14)

#define dma_rd_ch1_2_H  (0x188)
#define dma_rd_ch1_2_L  (0x184)

#define dma_rd_ch1_3_H  (0x198)
#define dma_rd_ch1_3_L  (0x194)

#define dma_rd_ch1_4_H  (0x1a8)
#define dma_rd_ch1_4_L  (0x1a4)


/*
dma_rd_ch2_1_64bit = dma_rd_ch2_1_H(0xc8)  + dma_rd_ch2_1_L(0xc4)
dma_rd_ch2_2_64bit = dma_rd_ch2_2_H(0x288) + dma_rd_ch2_2_L(0x284)
dma_rd_ch2_3_64bit = dma_rd_ch2_3_H(0x298) + dma_rd_ch2_3_L(0x294)
dma_rd_ch2_4_64bit = dma_rd_ch2_4_H(0x2a8) + dma_rd_ch2_4_L(0x2a4)
*/
#define dma_rd_ch2_1_H  (0xc8)
#define dma_rd_ch2_1_L  (0xc4)

#define dma_rd_ch2_2_H  (0x288)
#define dma_rd_ch2_2_L  (0x284)

#define dma_rd_ch2_3_H  (0x298)
#define dma_rd_ch2_3_L  (0x294)

#define dma_rd_ch2_4_H  (0x2a8)
#define dma_rd_ch2_4_L  (0x2a4)


/*
dma_rd_ch3_1_64bit = dma_rd_ch3_1_H(0xd8)  + dma_rd_ch3_1_L(0xd4)
dma_rd_ch3_2_64bit = dma_rd_ch3_2_H(0x388) + dma_rd_ch3_2_L(0x384)
dma_rd_ch3_3_64bit = dma_rd_ch3_3_H(0x398) + dma_rd_ch3_3_L(0x394)
dma_rd_ch3_4_64bit = dma_rd_ch3_4_H(0x3a8) + dma_rd_ch3_4_L(0x3a4)
*/
#define dma_rd_ch3_1_H  (0xd8)
#define dma_rd_ch3_1_L  (0xd4)

#define dma_rd_ch3_2_H  (0x388)
#define dma_rd_ch3_2_L  (0x384)

#define dma_rd_ch3_3_H  (0x398)
#define dma_rd_ch3_3_L  (0x394)

#define dma_rd_ch3_4_H  (0x3a8)
#define dma_rd_ch3_4_L  (0x3a4)


/*
dma_rd_ch4_1_64bit = dma_rd_ch4_1_H(0xe8)  + dma_rd_ch4_1_L(0xe4)
dma_rd_ch4_2_64bit = dma_rd_ch4_2_H(0x488) + dma_rd_ch4_2_L(0x484)
dma_rd_ch4_3_64bit = dma_rd_ch4_3_H(0x498) + dma_rd_ch4_3_L(0x494)
dma_rd_ch4_4_64bit = dma_rd_ch4_4_H(0x4a8) + dma_rd_ch4_4_L(0x4a4)
*/
#define dma_rd_ch4_1_H  (0xe8)
#define dma_rd_ch4_1_L  (0xe4)

#define dma_rd_ch4_2_H  (0x488)
#define dma_rd_ch4_2_L  (0x484)

#define dma_rd_ch4_3_H  (0x498)
#define dma_rd_ch4_3_L  (0x494)

#define dma_rd_ch4_4_H  (0x4a8)
#define dma_rd_ch4_4_L  (0x4a4)


/*
dma_rd_size_1 (0x18)
dma_rd_size_2 (0xcc)
dma_rd_size_3 (0xdc)
dma_rd_size_4 (0xec)

4.
FPGA������ͨ��������棬ͬʱ4��ͨ�������ٲã�ѡ��һ��ͨ�����ж�����䡣

5.
���ڸ��ݵ�ǰ��������ͨ���������ö���������
dma_rd_cmd_1 (0x10) =0x1
dma_rd_cmd_2 (0xc0) =0x1
dma_rd_cmd_3 (0xd0) =0x1
dma_rd_cmd_4 (0xe0) =0x1
�����㡣
*/
#define dma_rd_size_1  (0x80)
#define dma_rd_size_2  (0x180)
#define dma_rd_size_3  (0xdc)
#define dma_rd_size_4  (0xec)


// write-0 & 1
#define dma_rd_cmd_1  (0x10)
#define dma_rd_cmd_2  (0xc0)
#define dma_rd_cmd_3  (0xd0)
#define dma_rd_cmd_4  (0xe0)

/*
7.
���ڶ˿ɲ�ѯ��ͨ���Ķ���ɴ�����
dma_rd_complete_cnt1 (0xf0)
ͨ��1��ɶ��Ĵ���
dma_rd_complete_cnt2 (0xf4)
ͨ��2��ɶ��Ĵ���
dma_rd_complete_cnt3 (0xf8)
ͨ��3��ɶ��Ĵ���
dma_rd_complete_cnt4 (0xfc)
ͨ��4��ɶ��Ĵ���
*/
#endif




/////////////////////////////////////////////////////////////////////
//
#if 1
//
//  kernel kmalloc ddr space
//
//#define BLK_CNT_4M     (128)  // 128 *4M = 512M
#define BLK_CNT_4M     (64)  // 64 *4M = 256M

#define BUF_4_FRAME    (4)    // ÿͨ�� 4frame ����
#endif
//
/////////////////////////////////////////////////////////////////////

#if 1
/*
ͼ��ͨ��       	�ֱ���	          �洢�ռ�������1MBΪ��С��λ��	               ʵ�ʷ���       idx_blk_4M   < ÿͨ�� 4frame ���� >
--------------------------------------------------------------------------------------------------------------
1 - TGIR-W/N	1280��1024��16bit@50fps��Ĭ��ģʽ��	           3MB	    4MB       0 ~ 3    (4 * 4M)   - chn-1  (fpga-->ft)
	        	640��512��16bit@100fps��΢ɨģʽ��	           1MB	
	        
2 - TGIR-SW	    640��512��16bit@50fps	                   1MB	    1MB       4        (1 * 4M)   - chn-2

3 - NVIR	    640��512��16bit@50fps                    1MB	    1MB       5        (1 * 4M)   - chn-3
 
4 - SWIR	    640��512��16bit@50fps	                   1MB	    1MB       6        (1 * 4M)   - chn-4

5 - TV-SW	    1280��1024��8bit@50fps������ģʽ��	           2MB	    8MB       8 ~ 15   (8 * 4M)   - chn-5
	        	2448��2048��8bit@25fps�����ģʽ�����ã�	5MB	
	        
6 - TV-W	    1280��1024��8bit@50fps������ģʽ��	           2MB	    8MB       16 ~ 23   (8 * 4M)   - chn-6
	        	2448��2048��8bit@25fps�����ģʽ�����ã�	5MB	
	        
7 - TV-N	    1280��1024��8bit@50fps������ģʽ��	           2MB	    16MB      24 ~ 39   (16 * 4M)   - chn-7
	        	4096��3000��8bit@10fps�����ģʽ��             12MB	
	        
-----------------------------------------------------------------------------------------------------------------	        
SDI��ƵVideo-OUT��	1920��1080��16bit@50fps��YUV422��ʽ��	         8MB	8MB   40 ~ 41      (2 * 4M)   - tx-1  (ft-->fpga)

������Ƶ	           1920��1080��16bit@25fps��YUV422��ʽ��	     8MB	8MB   42 ~ 43      (2 * 4M)   - tx-2

���и���ͼƬ	           4096��3000��8bit@10fps	                 12MB	16MB  44 ~ 47      (4 * 4M)   - tx-3

PAL��Ƶ	           720��576��32bit��RGBA��ʽ����֡�ʴ�����	2MB	            2MB   48           (1 * 4M)   - tx-4
*/

//
// -- ft<--fpga --
//
#define  idx_chn1_GIR_WN    (0)        // 0 ~ 3    (4 * 4M) 
#define  size_chn1_GIR_WN_0 (SIZE_3M)
#define  size_chn1_GIR_WN_1 (SIZE_1M)

#define  idx_chn2_TGIR_SW  (4)         // 4        (1 * 4M)
#define  size_chn2_TGIR_SW (SIZE_1M)

#define  idx_chn3_NVIR     (5)         // 5        (1 * 4M) 
#define  size_chn3_NVIR    (SIZE_1M)

#define  idx_chn4_SWIR     (6)         //  6       (1 * 4M)
#define  size_chn4_SWIR    (SIZE_1M)

#define  idx_chn5_TV_SW    (8)         // 8 ~ 15   (8 * 4M)
#define  size_chn5_TV_SW_0 (SIZE_2M)
#define  size_chn5_TV_SW_1 (SIZE_5M)

#define  idx_chn6_TV_W     (16)        //16 ~ 23   (8 * 4M)
#define  size_chn6_TV_W_0  (SIZE_2M)
#define  size_chn6_TV_W_1  (SIZE_5M)

#define  idx_chn7_TV_N     (24)        // 24 ~ 39   (16 * 4M) 
#define  size_chn7_TV_N_0  (SIZE_2M)
#define  size_chn7_TV_N_1  (SIZE_12M)
#endif

#if 1
/*
-----------------------------------------------------------------------------------------------------------------	        
SDI��ƵVideo-OUT��	1920��1080��16bit@50fps��YUV422��ʽ��	         8MB	8MB   40 ~ 41      (2 * 4M)   - tx-1  (ft-->fpga)

������Ƶ	           1920��1080��16bit@25fps��YUV422��ʽ��	     8MB	8MB   42 ~ 43      (2 * 4M)   - tx-2

���и���ͼƬ	           4096��3000��8bit@10fps	                 12MB	16MB  44 ~ 47      (4 * 4M)   - tx-3

PAL��Ƶ	           720��576��32bit��RGBA��ʽ����֡�ʴ�����	2MB	            2MB   48           (1 * 4M)   - tx-4
*/
//
// -- ft-->fpga --
//
#define  idx_tx1_SDI      (40)       // 40 ~ 41      (2 * 4M) 
#define  size_tx1_SDI     (SIZE_8M)

#define  idx_tx2_VIDEO    (42)       // 42 ~ 43      (2 * 4M)
#define  size_tx2_VIDEO   (SIZE_8M)

#define  idx_tx3_PIC      (44)       // 44 ~ 47      (4 * 4M) 
#define  size_tx3_PIC     (SIZE_16M)

#define  idx_tx4_PAL      (48)       // 48           (1 * 4M)
#define  size_tx4_PAL     (SIZE_2M)

#define USRSPACE_SET_DATA
#endif


#if 1
//
// extern 
//
extern void printk_dbg(unsigned char * buf, int count);
extern void printk_dbg2(unsigned char * buf, int start, int count);

extern void kmalloc_dma_init_all(void);
extern void kmalloc_dma_rx_start_all(void);

extern unsigned long offset_to_phys_all(unsigned int offset);
extern unsigned long offset_to_virt_all(unsigned int offset);
extern int fpga_share_mem_mmap_all(struct vm_area_struct *vma);
extern unsigned long  virt_addr_kern_get(int idx);
extern unsigned long  phys_addr_kern_get(int idx);
extern void iounmap_all(void);

#endif


//
// chn-1
//
#define CHN1_OPEN
#ifdef CHN1_OPEN
extern void kmalloc_dma_rx_start_chn_1(void);
extern void irq_dma_rx_start_chn_1(void);
#endif


//
// chn-2
//
#define CHN2_OPEN
#ifdef CHN2_OPEN
extern void kmalloc_dma_rx_start_chn_2(void);
extern void irq_dma_rx_start_chn_2(void);
#endif

//
// chn-3
//
#define CHN3_OPEN
#ifdef CHN3_OPEN
extern void kmalloc_dma_rx_start_chn_3(void);
extern void irq_dma_rx_start_chn_3(void);
#endif

//
// chn-4
//
#define CHN4_OPEN
#ifdef CHN4_OPEN
extern void kmalloc_dma_rx_start_chn_4(void);
extern void irq_dma_rx_start_chn_4(void);
#endif

//
// chn-5
//
#define CHN5_OPEN
#ifdef CHN5_OPEN
extern void kmalloc_dma_rx_start_chn_5(void);
extern void irq_dma_rx_start_chn_5(void);
#endif

//
// chn-6
//
#define CHN6_OPEN
#ifdef CHN6_OPEN
extern void kmalloc_dma_rx_start_chn_6(void);
extern void irq_dma_rx_start_chn_6(void);
#endif

//
// chn-7
//
#define CHN7_OPEN
#ifdef CHN7_OPEN
extern void kmalloc_dma_rx_start_chn_7(void);
extern void irq_dma_rx_start_chn_7(void);
#endif


#if 1

extern void irq_dma_tx_start_chn_1(void);
extern void irq_dma_tx_start_chn_2(void);
extern void irq_dma_tx_start_chn_3(void);
extern void irq_dma_tx_start_chn_4(void);
#endif

#endif  /*_IOCTL_DRV_USR_H_*/

